Netlist Modifier for Implicit-style VHDL 1.0


Date Added:15 May, 2013

Author: Modify-edf

Category: Home & Education  >  Science



This Program will modify the netlist(edf file) generated by a vhdl synthesis tool of a Implicit style VHDL Model, so that the propagation delay caused by signals are removed, so that the post synthesis do match the ideal and pre-synthesis analysis.

Systems: Windows

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